Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same

ABSTRACT

A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

CROSS-REFERENCE

This application is a divisional of application Ser. No. 13/749,186filed Jan. 24, 2013, (Atty. Docket No. 2012-0977/24061.2331). Thispatent is related to the following patents, the disclosures of which arehereby incorporated by reference:

-   -   A Vertical Tunneling Field-Effect Transistor Cell And        Fabricating The Same, Ser. No. 13/745,225 filed Jan. 18, 2013,        (Atty. Docket No. 2012-0976/24061.2328);    -   A Vertical Tunneling Field-Effect Transistor Cell And        Fabricating The Same, Ser. No. 13/745,459 filed Jan. 18, 2013,        (Atty. Docket No. 2012-0974/24061.2324).    -   A Vertical Tunneling Field-Effect Transistor Cell And        Fabricating The Same, Ser. No. 13/745,579 filed Jan. 18, 2013,        (Atty. Docket No. 2012-0978/24061.2330);

BACKGROUND

The semiconductor integrated circuit industry has experienced rapidgrowth in the past several decades. Technological advances insemiconductor materials and design have produced increasingly smallerand more complex circuits. These material and design advances have beenmade possible as the technologies related to processing andmanufacturing have also undergone technical advances. In the course ofsemiconductor evolution, the number of interconnected devices per unitof area has increased as the size of the smallest component that can bereliably created has decreased.

However, as the size of the smallest component has decreased, numerouschallenges have risen. As features become closer, current leakage canbecome more noticeable, signals can crossover more easily, and powerusage has become a significant concern. The semiconductor integratedcircuit industry has produced numerous developments in effort tocontinue the process of scaling. One of the developments is thepotential replacement or supplementation of the conventional MOSfield-effect transistor by the tunneling field-effect transistor (TFET).

TFETs are promising devices that may enable further scaling of powersupply voltage without substantially increasing off-state leakagecurrents due to its sub-60 mV/dec subthreshold swing. However, existingTFETs have not been satisfactory in every respect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is a flowchart of an example method for fabricating asemiconductor device constructed according to various aspects of thepresent disclosure.

FIGS. 2-11 are cross-sectional views of an example semiconductor deviceat fabrication stages constructed according to the method of FIG. 1.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the disclosure. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the performance of a first process before a second process in thedescription that follows may include embodiments in which the secondprocess is performed immediately after the first process, and may alsoinclude embodiments in which additional processes may be performedbetween the first and second processes. Various features may bearbitrarily drawn in different scales for the sake of simplicity andclarity. Furthermore, the formation of a first feature over or on asecond feature in the description that follows may include embodimentsin which the first and second features are formed in direct contact, andmay also include embodiments in which additional features may be formedbetween the first and second features, such that the first and secondfeatures may not be in direct contact.

FIG. 1 is a flowchart of one embodiment of a method 100 of fabricatingone or more TFET devices according to aspects of the present disclosure.The method 100 is discussed in detail below, with reference to a TFETdevice 200 shown in FIGS. 2-11 for the sake of example.

Referring to FIGS. 1 and 2, the method 100 begins at step 102 byproviding a substrate 210. The substrate 210 includes silicon. Inalternative embodiments, the substrate 210 may include germanium,silicon germanium, gallium arsenide, silicon carbide, indium arsenide,indium phosphide, gallium arsenic phosphide, gallium indium, or otherappropriate semiconductor materials. Alternatively and for someembodiments, the substrate 210 may include an epitaxial layer. Forexample, the substrate 210 may have an epitaxial layer overlying a bulksemiconductor. Further, the substrate 210 may be strained forperformance enhancement. For example, the epitaxial layer may include asemiconductor material different from those of the bulk semiconductorsuch as a layer of silicon germanium overlying bulk silicon or a layerof silicon overlying a bulk silicon germanium formed by a processincluding selective epitaxial growth (SEG). Furthermore, the substrate210 may include a semiconductor-on-insulator (SOI) structure such as aburied dielectric layer. Also alternatively, the substrate 210 mayinclude a buried dielectric layer such as a buried oxide (BOX) layer,such as that formed by a method referred to as separation byimplantation of oxygen (SIMOX) technology, wafer bonding, SEG, or otherappropriate methods. In fact various embodiments may include any of avariety of substrate structures and materials. The substrate 210 mayalso include various p-type doped regions and/or n-type doped regions,implemented by a process such as ion implantation and/or diffusion.Those doped regions include n-well and p-well.

The method 100 proceeds to step 104 by etching the substrate 210 to forma frustoconical protrusion structure 220 with a first height h₁, whichprotrudes out of the plane of substrate 210. The frustoconicalprotrusion structure 220 is referred as a core structure 220. The corestructure 220 may be formed by lithography and etching processes. In oneembodiment, a hard mask layer 215 is deposited on the substrate 210first. The hard mask 215 includes silicon oxide, silicon nitride,silicon oxynitride, or any other suitable dielectric material. The hardmask 215 may be patterned by lithography and etching processes to definethe core structure 220 with a first width w₁. The substrate 210 isetched by using the patterned hard mask 215 as an etching mask to formthe core structure 220. The etch process may include wet etch, dry etch,or a combination thereof. The core structure 220 can be formed withsidewalls having an angle a with the planar surface of the substrate 210ranging from approximately 45 degrees to around 90 degrees.

In one embodiment, the core structure 220 is formed as a cylinder shape.Alternatively, the core structure 220 is formed as square-column, ovalcylinder, rectangular column, hexagonal column, or other polygon-columnshape.

Referring to FIGS. 1 and 3, the method 100 proceeds to step 106 byforming isolation features 230 on the substrate 210, including betweeneach core structure 220. The isolation features 230 may include similaror different structures formed by using different processingtechnologies. In one embodiment, the isolation features 230 are shallowtrench isolation (STI) features. The formation of a STI may includeetching a trench in the substrate 210 and filling in the trench withinsulator materials such as silicon oxide, silicon nitride, or siliconoxynitride. The filled trench may have a multi-layer structure such as athermal oxide liner layer with silicon nitride filling the trench.

Referring to FIGS. 1 and 4, the method 100 proceeds to step 108 byforming a drain region 310 with a second width w₂ on the substrate 210.The second width w₂ is substantially larger than the first width w₁. Inone embodiment, the drain region 310 is concentric with the corestructure 220 and isolated to each other by the isolation feature 230.The drain region 310 is formed by doping a predetermined top portion ofthe substrate 210 by a suitable technique, such as implantation with apatterned photo resist as an implantation mask. In the presentembodiment, the drain region 310 is adjacent to the core structure 220and between the isolation features 230. For a p-type TFET, the drainregion 310 may be doped with p-type dopants, such as boron or BF₂. Foran n-type TFET, the drain region 310 may be doped with n-type dopants,such as phosphorus, arsenic, or combinations thereof. After theimplantation, one or more annealing processes may be performed fordopant activation. The annealing processes may include rapid thermalanneal (RTA), laser anneal, or other suitable annealing process. As anexample, high-temperature anneal includes a “spike” annealing processthat has a very short time duration. During the formation, the dopant isdiffused up to a bottom portion of the core structure 220 with a secondheight of h₂, referred as to a raised drain region 310.

Referring to FIGS. 1 and 5, the method 100 proceeds to step 110 byforming a first isolation dielectric layer 410 over the drain region 310by deposition and recess processes. The first isolation dielectric layer410 includes silicon oxide, silicon nitride, silicon carbide, oxynitrideor other suitable materials. The first isolation dielectric layer 410may include a single layer or multiple layers. The first isolationdielectric layer 410 is deposited by a suitable technique, such aschemical vapor deposition (CVD), atomic layer deposition (ALD), physicalvapor deposition (PVD), thermal oxidation, or combinations thereof. Inthe present embodiment, the isolation dielectric layer 410 is etchedback to a third height h₃, which is substantial less than the secondheight h₂of the raised drain region 310. The first isolation dielectriclayer 410 may be recessed by a selective dry etch, a selective wet etch,or a combination thereof.

Referring to FIGS. 1 and 6, the method 100 proceeds to step 112 byforming a gate stack 510. The gate stack 510 includes a planar portion512, which is parallel to the surface of substrate 210 and over thefirst isolation dielectric layer 410, and a gating surface, which wrapsaround a middle portion of the core structure 220. The planar portionmay be asymmetric to the core structure 220. A total width of the gatestack 510, a third width w₃, is substantially larger than the firstwidth w₁ of the core structure 220 and less than the second width w₂ ofthe drain region 310. In one embodiment, the out-of-plane gating surfaceof gate stack 510 overlaps a portion of the raised drain region 310.

The gate stack 510 is formed by any suitable process or processes. Forexample, the gate stack 510 is formed by a procedure includingdepositing, photolithography patterning, and etching processes. Thedeposition processes include CVD, PVD, ALD, metalorganic CVD (MOCVD),other suitable methods, and/or combinations thereof. Thephotolithography patterning processes include photoresist coating (e.g.,spin-on coating), soft baking, mask aligning, exposure, post-exposurebaking, developing the photoresist, rinsing, drying (e.g., hard baking),other suitable processes, and/or combinations thereof. The etchingprocess includes a dry etch, a wet etch, or a combination of dry etchand wet etch. The dry etching process may implement fluorine-containinggas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₂F₆), chlorine-containing gas(e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃), bromine-containing gas (e.g., HBrand/or CHBR₃), iodine-containing gas, other suitable gases and/orplasmas, and/or combinations thereof. The etching process may include amultiple-step etching to gain etch selectivity, flexibility and desiredetch profile.

In one embodiment, the gate stack 510 is a high-k (HK)/metal gate (MG).The HK/MG includes a gate dielectric layer 520 and a MG 530. The gatedielectric layer 520 may include an interfacial layer (IL) and a high-k(HK) dielectric layer. The IL includes oxide, HfSiO and oxynitride. TheHK dielectric layer may include LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃(STO), BaTiO₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO,HfTiO, (Ba,Sr)TiO₃ (BST), Al₂O₃, Si₃N₄, oxynitrides (SiON), or othersuitable materials. The MG 530 may include a single layer or multilayers, such as a metal layer, a liner layer, a wetting layer, and anadhesion layer. The MG 530 may include Ti, Ag, Al, TiAlN, TaC, TaCN,TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or any suitablematerials.

In another embodiment, the gate stack 510 is a polysilicon gate stack.The polisilicon gate stack may include a gate dielectric layer and apolysilicon layer deposited over the gate dielectric layer. The gatedielectric layer includes silicon oxide, silicon nitride, or any othersuitable materials.

Referring to FIGS. 1 and 7, the method 100 proceeds to step 114 byforming a second isolation dielectric layer 610 over the first isolationdielectric layer 410, including over the planar portion of the gatestack. The second isolation dielectric layer 610 is similar in manyrespects to those discussed above in association with the firstisolation dielectric layer 410 in FIG. 5. The second isolationdielectric layer 610 is etched back to expose a predetermined height ofa top portion of the gating surface of gate stack 510. In oneembodiment, the predetermined height is substantially larger than athickness of the hard mask layer 215.

Referring to FIGS. 1 and 8, the method 100 proceeds to step 116 byremoving a top portion of the gating surface of the gate stack 510 toexpose a top portion of the core structure 220 with a fourth height h₄.The top portion of the gating surface of the gate stack 510 may beremoved by a selective dry etch, a selective wet etch, a combinationthereof, or other suitable processes. The hard mask layer 215 is alsoremoved at the same etch process or at an extra etch process. In oneembodiment, the gating surface of the gate stack 510 above the secondisolation dielectric layer 610 is removed.

Referring to FIGS. 1 and 9, the method 100 proceeds to step 118 byforming a source region 710 in the top portion of the core structure220. In one embodiment, the source region 710 is formed byphotolithography patterning and implantation, which is similar in manyrespects to those discussed above in association with the drain region310 in FIG. 4. The source region 710 has a different dope type than thedrain region 310. In another embodiment, the core structure 220 isrecessed first and then the source region 710 is formed as the topportion of the recessed core structure 220 by photolithographypatterning and implantation. In yet another embodiment, a semiconductormaterial is epitaxially grown on the recessed core structure 220. Thesemiconductor material layer includes element semiconductor materialsuch as germanium (Ge) or silicon (Si); or compound semiconductormaterials, such as gallium arsenide (GaAs), aluminum gallium arsenide(AlGaAs); or semiconductor alloy, such as silicon germanium (SiGe),gallium arsenide phosphide (GaAsP). The epitaxial processes include CVDdeposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-highvacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitableprocesses. The S/D features may be formed by one or more epitaxy orepitaxial (epi) processes. The source region 710 may be in-situ dopedduring the epitaxy process. In one embodiment, the source region 710 isnot in-situ doped, an implantation process (i.e., a junction implantprocess) is performed to dope the source region 710.

Referring to FIGS. 1 and 10, the method 100 proceeds to step 120 bydepositing a third isolation dielectric layer 810 over the secondisolation dielectric layer 610, including over the source region 710.The third isolation dielectric layer 810 is similar in many respects tothose discussed above in association with the first isolation dielectriclayer 410 in FIG. 3. Additionally, a CMP process is performed toplanarize the top surface of the third isolation dielectric layer 810.

Referring to FIGS. 1 and 11, the method 100 proceeds to step 122 byforming a source contact 910, gate contact 920 and drain contact 930.Contacts 910, 920 and 930 may be formed by lithography patterning andetch processes. The photolithography patterning processes includephotoresist coating (e.g., spin-on coating), soft baking, mask aligning,exposure, post-exposure baking, developing the photoresist, rinsing,drying (e.g., hard baking), other suitable processes, and/orcombinations thereof. The etching process includes a dry etch, a wetetch, or a combination of dry etch and wet etch. The dry etching processmay implement fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3,and/or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/orBCl3), bromine-containing gas (e.g., HBr and/or CHBR3),iodine-containing gas, other suitable gases and/or plasmas, and/orcombinations thereof. The etching process may include a multiple-stepetching to gain etch selectivity, flexibility and desired etch profile.

In the present embodiment, the contact etch is configured to have anadequate selectivity with respect to source region 710, the gate stack510 and the drain region 310. In one embodiment, the gate contact 920 isformed at the planar portion of the gate stack 510. Alternatively, thegate contact 920 is formed at the planar portion of the gate stack 510and overlay at least a portion (925) of the second isolation dielectriclayer 610 or a portion of both of first and second isolation dielectriclayers 610 and 410. The drain contact 930 is formed at the drain region310 and overlay at least a portion (935) of the isolation feature 230 byremoving the portion 935 of the isolation feature 230 in the contactetch. In the drain contact 930, a portion of the drain region 310 insidethe isolation feature 230 is exposed, which enlarges drain contactinterface and may result in contact resistance reduction. By forming thegate contact 920 in the planar region of the gate stack 510 and theportion 925 of the isolation dielectric layer, and the drain contact 930in the drain region 310 and the portion 935 of the isolation feature 230together, a required active area of the device 200 may be reduced and aconstrain of contact lithography process may be relaxed.

The TFET device 200 may undergo further CMOS or MOS technologyprocessing to form various features and regions known in the art. Forexample, subsequent processing may form various vias/lines andmultilayers interconnect features (e.g., metal layers and interlayerdielectrics) on the substrate 210, configured to connect the variousfeatures or structures of the TFET device 200. For example, a multilayerinterconnection includes vertical interconnects, such as conventionaland horizontal interconnects, such as metal lines. The variousinterconnection features may implement various conductive materialsincluding copper, tungsten, and/or silicide.

Additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced, eliminated, ormoved around for additional embodiments of the method 100.

Based on the above, the present disclosure offers a TFET deviceemploying a gate contact overlay on the isolation dielectric layer anddrain contact overlay on the isolation feature and a method offabrication. By overlay on the isolation feature, the drain contactresistance is reduced by an enlarged contact interface, a requiredactive area of a device is reduced by saving gate and drain contact areaand contact lithography process constrains are relaxed. The method isquite feasible to an existing TFET fabrication.

The present disclosure provides many different embodiments of TFETdevice that provide one or more improvements over other existingapproaches. In one embodiment, the TFET device includes a substrate, afrustoconical protrusion structure disposed over the substrate andprotruding out of the plane of substrate, a drain region disposed overthe substrate adjacent to the frustoconical protrusion structure andextending to a bottom portion of the frustoconical protrusion structureas a raised drain region. The TFET device also includes an isolationfeature between drain regions, a gate stack disposed over the substrate.The gate stack has a planar portion, which is parallel to the surface ofsubstrate and a gating surface, which wraps around a middle portion ofthe frustoconical protrusion structure, including overlapping with theraised drain region. The TFET device also includes a source regiondisposed as a top portion of the frustoconical protrusion structure,including overlapping with a top portion of the gating surface of thegate stack, an isolation dielectric layer disposed over the sourceregion, the gate stack and between the planar portion of the gate stackand the drain region. TFET device also includes a gate contact formed onthe planar portion of the gate stack and extending to a portion of theisolation dielectric layer and a drain contact formed on the drainregion and extending to a portion of the isolation feature.

In another embodiment, a vertical TFET device includes a semiconductorsubstrate, a frustoconical protrusion cylinder disposed over thesubstrate and protruding out of the plane of semiconductor substrate, asource region as a top portion of the frustoconical protrusion cylinder,a high-k/metal gate (HK/MG) disposed over the semiconductor substrate.The HK/MG has a planar portion, which is parallel to the surface ofsemiconductor substrate and a gating surface, which wraps around amiddle portion of the frustoconical protrusion cylinder, includingoverlapping with the source region. The TFET device also includes adrain region disposed over the semiconductor substrate adjacent to thefrustoconical protrusion cylinder and extending to a bottom portion ofthe frustoconical protrusion cylinder as a raised drain region, anisolation feature disposed between the drain regions, an isolationdielectric layer disposed over the source region, the gate stack and thedrain region, including between the planar portion of the HK/MG and thedrain region and a drain contact disposed on the drain region andextends to a portion of the isolation feature.

In yet another embodiment, a method of fabricating a semiconductordevice includes providing a substrate, etching the substrate to form aprotrusion on a surface of the substrate, forming isolation feature onthe substrate, doping a portion of the substrate adjacent to theprotrusion to form a drain region between isolation features, includingextending to a lower portion of the protrusion to form a raised drainregion.

The method also includes forming a first isolation dielectric layer overthe drain region, forming gate stack having a planar portion over thedrain region, which is parallel to the surface of substrate, and agating surface, which wraps around a middle portion of the protrusion,including overlapping with the raised drain region. The method yet alsoincludes forming a second isolation dielectric layer over the planarportion of the gate stack and the drain region, recessing a portion ofthe gating surface of the gate stack to expose a top portion of theprotrusion, forming a source region on the top portion of the protrusionwith a different dope type than the drain region, including overlappingwith the gating surface of the gate stack. The method yet also includesforming a third isolation dielectric layer over the source region, thegate stack and the second isolation dielectric layer, forming a draincontact on the drain region and a portion of the isolation featuretogether and simultaneously with the drain contact formation, forming agate contact on the planar portion of the gate stack and extending to aportion of the isolation dielectric layer, and a source contact on thesource region.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.For example, source and drain regions are often swapped with anappropriate process modification/interchanging, depending on thetransistor's eventual use and electrical configuration. Therefore, theterms “source” and “drain” are deemed to be interchangeable under suchcircumstances. Those skilled in the art should also realize that suchequivalent constructions do not depart from the spirit and scope of thepresent disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method for forming a field effect transistor(FET), the method comprising: providing a substrate; etching thesubstrate to form a protrusion on a surface of the substrate; formingisolation features on the substrate; doping a portion of the substrateadjacent to the protrusion to form a drain region between the isolationfeatures, including doping a lower portion of the protrusion to form araised drain region; forming a first isolation dielectric layer over thedrain region; forming a gate stack having a planar portion over thedrain region, which is parallel to the surface of the substrate and hasa sidewall and a gating surface, which wraps around a middle portion ofthe protrusion and which overlaps with the raised drain region; forminga second isolation dielectric layer over the planar portion of the gatestack and the raised drain region; recessing a portion of the gatingsurface of the gate stack to expose a top portion of the protrusion;forming a source region on the top portion of the protrusion with adifferent doping type than the drain region, the source regionoverlapping with the gating surface of the gate stack; forming a thirdisolation dielectric layer over the source region, the gate stack andthe second isolation dielectric layer; forming a drain contact on thedrain region and a portion of one of the isolation features together;and simultaneously with the drain contact formation, forming a gatecontact on the planar portion of the gate stack and the sidewall of theplanar portion of the gate stack, the gate contact extending through aportion of the isolation dielectric layer, and forming a source contacton the source region.
 2. The method of claim 1, wherein the portion ofthe one of the isolation features is removed to expose a portion of thedrain region in the drain contact.
 3. The method of claim 1, furthercomprising forming the middle portion of the protrusion out of the samematerial as the substrate.
 4. The method of claim 1, wherein theprotrusion structure is formed as a cylinder.
 5. The method of claim 1,wherein the protrusion structure is formed as one of a square-columnstructure and a hexagonal-column structure.
 6. The method of claim 1,wherein the protrusion structure is formed as an oval-cylinderstructure.
 7. The method of claim 1, wherein forming the gate stackincludes forming the gate stack from a high-k/metal material.
 8. Amethod for forming a field effect transistor (FET), the methodcomprising: providing a substrate having a protrusion structure formedon a planar surface of the substrate, the protrusion structure having atop portion, a middle portion, and a bottom portion; forming anisolation structure in the substrate; forming a drain region in thesubstrate and in the bottom portion of the protrusion structure; forminga gate structure over the drain region and on a sidewall of theprotrusion structure, the gate structure surrounding the protrusionstructure and having a planar region extending away from the protrusionstructure and having a sidewall; forming a source region in the topportion of the protrusion structure; forming a drain contact landing ona portion of the drain region and on a portion of the isolationstructure; forming a gate contact landing on a portion of the planarregion of the gate structure and on a portion of the sidewall of theplanar region of the gate structure; and forming a source contactlanding on the source region.
 9. The method of claim 8, wherein the gatestructure includes a dielectric layer, a high-k gate dielectric, and ametal gate layer.
 10. The method of claim 8, further comprising formingan isolation dielectric layer over the drain region.
 11. The method ofclaim 10, wherein the isolation dielectric layer is a first isolationdielectric layer that is formed beneath the gate structure, the methodfurther comprising: forming a second isolation dielectric layer over theplanar region of the gate structure and beneath a top surface of thegate structure; and forming a third isolation dielectric layer over thesecond isolation dielectric layer and over the gate structure.
 12. Themethod of claim 8, further comprising removing the portion of the drainregion so that the drain contact landing on the portion of the drainregion is in contact with a sidewall of the drain region.
 13. The methodof claim 8, wherein the middle portion of the protrusion structure iscomprised of the same material as the substrate.
 14. The method of claim8, wherein the protrusion structure is formed as a cylinder.
 15. Amethod for forming a field effect transistor (FET), the methodcomprising: receiving a substrate, the substrate having a protrusionformed thereon; forming an isolation structure in the substrate, theisolation structure surrounding the protrusion; forming a drain featurein the substrate, the drain feature extending into a bottom portion ofthe protrusion; forming a source feature in a top portion of theprotrusion; forming a gate feature on a sidewall of the protrusion suchthat the gate feature is in contact with the top portion of theprotrusion and the bottom portion of the protrusion, the gate featurehaving a planar portion extending laterally away from the protrusionparallel to the drain region and having a sidewall; forming a sourcecontact on the source region; forming a drain contact on the drainregion and overlapping with the isolation structure; and forming a gatecontact on the planar portion of the gate feature and in contact withthe sidewall of the gate feature.
 16. The method of claim 15, furthercomprising: forming a first isolation dielectric layer over the drainregion such that the gate feature is vertically separated from the drainregion by the first isolation dielectric layer; and forming a secondisolation dielectric layer over the gate feature.
 17. The method ofclaim 16, wherein the second isolation dielectric layer is in contactwith the sidewall of the planar portion of the gate feature.
 18. Themethod of claim 15, wherein the protrusion has a middle portioncomprised of the same material as the substrate.
 19. The method of claim15, further comprising removing a portion of the isolation structurethat is overlapped by the drain contact such that a portion of the draincontact overlapping with the isolation structure is in contact with thedrain region.
 20. The method of claim 15, wherein the gate contact andthe drain contact are formed on opposite sides of the protrusionstructure.